Decoder for interval encoded pulse pairs



Oct. 28, 1969 H. MEHRTENS DECODER FOR INTERVAL ENCODED PULSE PAIRS Filed June 14, 1968 JITTER REGISTER CLOCK REGISTER COIN. DET

United States US. Cl. 343-63 Claims ABSTRACT OF THE DISCLOSURE In the decoder of a secondary radar transponder a first interrogating pulse is delayed and tested for coincidence with a second interrogating pulse. In order to tighten up the tolerances within which detection of coincidence occurs the decoder takes account of the order in which the pulses are applied to the coincidence detector; only one pulse order is accepted as giving coincidence.

The present invention relates to secondary radar decoders which provide an output signal only when two pulses are separated by a predetermined time. Such decoders are used in secondary radar systems, in which, when two pulses separated by a certain time are received by a transponder in an aircraft, the transponder transmits return information concerning the aircraft. Different intervals between pulses can be used to obtain different items of information from the aircraft.

In decoding secondary radar ground station interrogations the fundamental problem is to detect the reception of a pulse pair whose leading edges are separated by a time interval corresponding to a predetermined mode of interrogation, which for the internationally agreed civil modes A, B, C, D, are respectively 8, 17, 21 and 25 ,uS. If a pulse pair corresponding to the mode selected and spaced within $0.2 us. of the nominal interval, should be received, then the transponder is caused to reply. If the spacing is in error by more than :1 ,us. then transponder replies should not occur.

A decoder ourently in use has two parallel shift registers. The two registers are clocked continuously at l mc./s. rates with a 0.5 as. time delay between the two clock lines. Each register is constructed from dual D flip-flops with the Q output of each stage connected to the D input of the succeeding stage. Information is transmitted from stage to stage on the positive-going edge of the clock waveforms. The decoder receives the first pulse (P of an encoded pair, and the second pulse (P from the transponder to which it is connected. In the internationally-specified three-pulse system a non-mode-defining pulse P for suppressing response to side-lobes of the interrogating aerial is always radiated 2 ,uS. after the pulse P but although this pulse may cause difficulties by capturing decoders of the type which employ counters, it is not of importance in the present description and is only mentioned to clarify the designation of the pulse P The pulses P and P are formed to have a nominal duration of 0.8 ,uS., and are fed to the D input of the first stages of both shift registers. Pulses may be propagated along either one or both shift registers depending on the atet relative timing of the 0.8 s. pulses and the 1 as. clock periods. Outputs are taken from the corresponding stages of both registers, after the appropriate delay, and are tested for coincidence with a pulse P The relative timing of the pulses P and P becomes distorted in the decoder, and can be regarded as an uncertainty in the timing of the leading edge of the pulse P hereinafter referred as jitter. The principle cause of jitter is the fact that the pulses P and P are asynchronous with the clock pulses but the delayed pulses P are necessary phase referenced to the clock pulses and can only occur at positions spaced by 0.5 .s. intervals. Pulling the P pulses into line with the clock pulses has the apparent effect of shifting the P pulses relative to the delayed P pulses by up to 0.5 [.LS. Decoding occurs not only when the leading edge of a delayed pulse P and that of a pulse P are exactly coincident, but also when their durations overlap. Thus not only are pulses spaced by the nominal time decoded but also those spaced by longer and shorter periods are decoded. The specification for decoders therefore has to be in the form that pulses whose leading edges are spaced by intervals in a certain range are certainly decoded, pulses whose leading edges are spaced by intervals in extensions at both ends of the range may be decoded, but pulses spaced by greater intervals must certainly not be decoded. Jitter extends, by the maximum extent of the jitter, the range of intervals over which decoding occurs, and can make this range too large for proper decoding. The object of this invention is to overcome the problem which thus exists.

According to the present invention there is provided a secondary radar pulse decoder for indicating when first and second interrogating pulses are separated by a predetermined time, comprising means for delaying the first pulse by the predetermined time and coincidence means responsive both to the concurrence of the delayed first pulse and the second pulse and to the order in which such pulses are applied to provide an output for triggering a transponder return only when the delayed first pulse and the second pulse are concurrent and a predetermined one of the delayed first pulse and the second pulse commences not later than the other one of these pulses.

By allowing decoding only when the pulse P (i.e. the pulse referred to immediately above as the second pulse) occurs after the delayed pulse P for example, the extension of the decoding range is reduced since only when P at 10 (in full lines) in its correct timing position, and advanced, will decoding occur.

Two embodiments of the invention will now be de scribed, by way of example, with reference to the accompanying drawings, in which:

FIG. 1 is a series of pulse diagrams showing how jitter affects decoding,

FIG. 2 is a block diagram of a coincidence detector,

FIG. 3 is a block diagram of a decoder according to the invention, and

FIG. 4 illustrates another coincidence detector.

Referring to FIG. 1, the problem caused by jitter will first be explained, in more detail. FIG. 1(a) shows a pulse P at 10 (in full lines) in its correct timing position, and FIG. 1(b) shows two delayed pulses P, at the extreme positions 11 and 12 which will allow decoding, since there is overlap with the pulse P FIG. 1(a) shows at 13 the range of leading edge positionsof pulses P which will allow decoding. The line 14 in FIG. 1(a) shows the position of the leading edge of the delayed pulse P if its leading edge is coincident with that of P \Nhen jitter occurs the pulse P may occur anywhere between positions and 16, and consequently decoding can occur with the pulses P at 11 and 12 shifted further to the positions shown in broken lines and decoding is extended to the range 17 in FIG. 1(a). Thus pulses outside the desired spacing may be decoded.

If decoding is allowed only when the pulse P occurs after the pulse P the range of decoding is reduced to that designated 18 in :FIG. 1(a) which just includes the case where the leading edges of the pulses P and P are coincident.

A logic circuit which detects coincident pulses but gives an output only when one pulse is applied after the other will now be described with reference to FIG. 2.

A NAND gate 20 has three input terminals, one connected to a terminal 21 to which the delayed pulses P extended in secondary radar applications to a duration of the order of 1.3 nsecs, are applied, another input terminal connected to a terminal 22 to which the pulses P are applied, and the third input terminal connected to a NAND gate 23. Hence the gate 20 can only open in the presence of both the pulses P and P A NAND gate 24 is coupled to receive input signals from the gate 23 and the terminal 21, while the gate 23 receives an input signal from the gate 24 and a NAND gate 25. The pulse P is passed through a NAND gate 26 which is used as an inverter, and with the pulse P is applied to the gate 25.

In the following description of the operation of the circuit of FIG. 2, signals which enable the NAND gates 20 to 26 are designated 1 and the absence of such signals is designated The output of a gate is 0 only when all inputs are 1.

When neither pulses P nor P is present, the gate 24 receives a O and applies a 1 to the gate 23. The gate 25' receives a 1 via the inverter 26 and a 0 from the terminal 21; thus a l is applied to the gate 23 whose output is therefore a 0. The gates 23 and 24 are then set to inhibit the gate 20'. The gates 23 and 24 constitute a bistable circuit and in the state in which the gate 23 provides 0 (and the gate 24 provides l) the gate 20 is inhibited. In the second state in which the gates 23 and 24 provide 1 and 0 respectively, the gate 20 is not inhibited. The bistable circuit can only be set to this second state when the gate 25 provides a 1, which requires the simultaneous presence of P delayed and the absence of P Considering the case when P occurs before P the pulse P is applied to the terminal 22, a O is applied to the gate 25 which is still not enabled and the gates 23 and 24 are unaffected. The arrival of a pulse P does not enable the gate 25 which still receives a O and a 1. The pulse P is also applied to the gate 24 but this also receives a 0 from the gate 23 and is not opened, and the gate 2% is not enabled. On the removal of the pulse P and P the gates return to their original conditions.

If a pulse P is applied before a pulse P the gate 25 is enabled, which closes the gate 23, applying a 1 to the gate 20. The gate 24 is also opened and it applies a 0 to the gate 23 changing the state of the gates 23 and 24. The application of a pulse P now opens the gate 20, closes the gate 25 and applies a 1 to the gate 23 which remains closed. On removal of the pulses the gates return to original states and the circuit is reset.

Hence the gate 20 is opened only when a pulse P is applied after a pulse P and these pulses are concurrent. The output from the gate 20 is terminated when either pulse P or P is removed.

While, for convenience of explanation, a direct connection from the terminal 21 to the gate 20 has been shown, this correction is in fact redundant. The gate 20 merely requires two inputs connected to the gate 23 and the terminal 22 respectively.

PEG. 3 shows the circuit of a decoder in which the coincidence circuit of FIG. 2 is designated as a block 38*. Pulses to be decoded are applied at a terminal 31, and are passed to two shift registers 32 and 33 which are supplied with out-of-phase clock pulses from a clock source 34. After a specified delay depending on the number of stages in the registers, delayed pulses appear at the outputs of the registers and are passed to the input 21 of the coincidence detector fill where they may or may not be concurrent with undelayed pulses applied direct from the input terminal 31 to the input 22. in a practical circuit the registers 32 and 33 would be tapped at points corresponding to the delays of the civil secondary radar modes A, B, C, and D, mentioned above, and separate coincidence circuits would be provided for each tapping point.

Thus it will be seen from FIG. 1 and the corresponding explanation of jitter, that the provision of the coincidence detector 30, reduces decoding errors.

Two registers have been shown in FIG. 3 since it is Well known to use two registers for reasons already mentioned. The coincidence detector can equally be used in a decoder employing one delay line only.

While the circuit of FIG. 2 has been used to indicate coincidence of P and P only when P commences not after P thus restricting decoding to the range 17 of FIG. 1(a), the connections to the terminals 21 and 22 in FIG. 3 could be interchanged so that coincidence is only indicated when P and P overlap and P commences not before P This would restrict decoding to the range indicated at 19 in FIG. 1(0).

The second embodiment of the invention utilizes the coincidence detector shown in FIG. 4 as the block 30 in FIG. 3, in place of the detector of FIG. 2. The coincidence detector in FIG. 4 comprises an edge-triggered bistable circuit 35, in the embodiment illustrated a D flip-flop. The terminal 21 for the delayed -P pulse is connected to the D input and the terminal 22 for P is connected to the clock input CP. The flip-flop will only switch it P delayed commences not after P and hence the Q output of the flip-flop will be exactly the same as the output of the gate 26 in FlG. 2. In either event this output is used to trigger the transponder return. The transponder circuits other than the decoder are of course not shown; they can be entirely conventional.

I claim:

1. In a secondary radar pulse decoder for indicating when first and second interrogating pulses are separated by a predetermined time, and comprising means for delaying the first pulse by the predetermined time and coincidence means responsive to the concurrence of the delayed first pulse and the second pulse, the improvement consisting in that the coincidence means is additionally responsive to the order in which the pulses are applied thereto to provide an output for triggering a transponder return only when the delayed first pulse and the second pulse are concurrent and a predetermined one of the delayed first pulse and the second pulse commences not later than the other one of these pulses.

2. A secondary radar pulse decoder according to claim 1, wherein the coincidence means comprise first means for indicating when the delayed first pulse and the second pulse are concurrent and second means for inhibiting the first means unless a predetermined one of the delayed first pulse and the second pulse commences not later than the other one of these pulses.

3. A secondary radar pulse decoder according to claim 2, wherein the said second means comprise a bistable circuit having first and second states, in the first of which the said first means is inhibited, an an input circuit to the bistable circuit for setting the bistable circuit to 1, wherein the means for delaying the first pulse com- 1 prises at least one shift register responsive to clock pulses.

References Cited UNITED STATES PATENTS 10/1961 Barber 343-6.8 11/ 1964 Allen 343-6.8 4/1965 Clock 3436.8 11/ 1968 Hirsch et a1. 3436.8 X

RODNEY D. BENNETT, JR. Primary Examiner O M. F. HUBLER, Assistant Examiner 

